The present invention relates generally to current mirror circuits, and more particularly to precision current mirror circuitry for use in voltage-to-current conversion applications with low power supply voltages.
FIG. 1 shows a conventional voltage-to-current conversion circuit 1 including a voltage-to-current converter 14 that includes an operational amplifier 2, a resistor 4, an N-channel transistor 3, and a conventional P-channel current mirror including P-channel current mirror transistors 6 and 7. The voltage Vin applied to the (+) input of operational amplifier 2 is reproduced across resistor 4, producing a current Iin that flows through transistors 3 and 6 and is equal to Vin divided by the resistance of resistor 4. The current through transistor 6, scaled by the channel-with-to-channel-length ratio of transistor 7 to that of transistor 6, is produced as Iout through the drain of transistor 7. However, this prior art voltage-to-current converter 1 circuit has a lack of voltage “headroom”. That is, if VDD becomes too low (e.g., approximately 1.8 volts for a threshold voltage VT of transistors 6 and 7 of approximately 1.0 volts), transistor 3 begins to “saturate”. In this case, the gate-to-source voltage, and hence also the drain-to source voltage, of transistor 6, is approximately 0.8 volts. If, for example, Vin is at approximately 1.0 volts, the source of transistor 3 is also equal to 800 millivolts, so the drain-source voltage of transistor 3 is “squeezed” to nearly 0 volts. Under these conditions transistor 3 therefore has very little voltage “headroom” in which to operate properly. As VDD is further reduced, the amplitude range of Vin becomes even further limited.
FIG. 2 shows a known voltage-to-current converter circuit 10 having increased voltage headroom. Voltage-to-converter circuit 14 is the same in FIG. 2 as in FIG. 1. Conductor 5 in FIG. 2 is not connected to the gates of current mirror transistors 6 and 7 as in FIG. 1, but instead is connected to the (+) input of an error amplifier 12, the output of which is connected by conductor 9 to the gates of current mirror transistors 6 and 7. The (−) input of error amplifier 12 is connected by conductor 8 to the drain of current mirror output transistor 7 and to the source of a P-channel cascode transistor 16. The output current Iout flows through current mirror output transistor 7, cascode transistor 16, and output conductor 17. A bias voltage Vbias is applied to the gate of cascode transistor 16. Vbias can be chosen so that the drain-source voltage of transistor 3 can operate without saturating, whereby voltage-to-current converter circuit 10 can operate with much less voltage headroom than the standard voltage-to-current converter circuit 1 of FIG. 1. Specifically, Vbias is set to equal a VGS (gate-to-source) voltage of transistor 3 plus a few hundred millivolts, so that conductor 8 is a few hundred millivolts below VDD.
Error amplifier 12 in FIG. 2 operates to balance the drain-source voltages of current mirror control transistor 6 and current mirror output transistor 7 and creates the gate voltage on conductor 9 needed to produce the correct amount of current in current mirror transistors 6 and 7. Specifically, error amplifier 12 servos the feedback loop so the voltage of conductor 5 is close to the voltage of conductor 8. Therefore, current mirror transistor 6 takes up only a few hundred millivolts of voltage headroom. This is a large improvement over the approximately 1 volt of voltage headroom required by current mirror transistor 6 in FIG. 1. That leaves plenty of voltage headroom for transistor 3 to operate.
The foregoing circuit resembles a two-stage amplifier including a feedback loop with error amplifier 12 as a first stage and current mirror transistor 6 and voltage-to-current converter 14 as a second stage, wherein a compensation capacitor 50 is coupled between the gate and drain of transistor 6, as proper compensation is required in the feedback loop to provide stable amplifier operation. As the magnitude of the current Iin changes from a very high value to a very low value, the transconductance gm of transistors 6 and 7 also decreases roughly proportionately to Iin, but the transconductance of error amplifier 12 remains relatively constant because its bias current remains constant. (Typically, error amplifier 12 has a fixed tail current and therefore a fixed gm.) As is well known to those skilled in the art, the larger the ratio of the gm of the current mirror (which can be considered to be amplifier stage) to the gm of error amplifier stage 12, the more stable the two-stage amplifier circuit is. Therefore, the circuit shown in FIG. 2 can become unstable for the very low values of Iin. Typically, Vin and Iin can vary by a factor of as much as one or two decades (i.e., 10 to 100). When the current level in current mirror input transistor 6 volts falls to a low enough value, the circuit can become unstable.
FIG. 3 shows a prior art voltage-to-current conversion circuit 20 circuit that provides circuit stability over a wide range of values of Iin. In FIG. 3, transistors 22 and 26 and current sources 24 and 28 constitute a common gate amplifier in which the sources of transistors 22 and 26 receive a differential input signal from conductors 5 and 8. Conductor 9 is a high impedance node that needs to be stabilized by compensation capacitor 50. Since conductor 9 is the only high impedance node in the control loop, it can be stabilized over a wide range of current levels. The currents through current sources 24 and 28 flow through current mirror transistors 6 and 7, respectively. A mismatch in the current sources 24 and 28 causes errors in the current flowing through current mirror output transistor 7. The mismatches between current sources 24 and 28 are due to ordinary semiconductor processing techniques, and reduce the voltage-to-current conversion accuracy of voltage-to-current converter 20, especially at low levels of Iin, wherein a particular mismatch can cause a large percentage error in the ratio between Iin and Iout and hence between Vin and Iout.
Thus, each of the prior art circuits shown in FIGS. 1–3 has particular benefits, but each also has its own shortcomings.
Thus, there is an unmet need for an improved, stable voltage-to-current conversion circuit that provides high precision with low power supply voltage.
There also is an unmet need for an improved, stable voltage-to-current conversion circuit that provides high precision at low power supply voltages and avoids inaccuracies due to mismatches in internal current sources caused by semiconductor processing variations.
There also is an unmet need for an improved, stable voltage-to-current conversion circuit that provides high precision with low supply voltages over a wide range of input voltage values and corresponding internal current levels.